As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a multi-gate field effect transistor (FET), including a fin FET (FinFET) and a gate-all-around (GAA) FET. In a GAA FET, a channel region is formed by a semiconductor wire wrapped with a gate dielectric layer and a gate electrode layer. Because the gate structure surrounds (wraps) the channel region on all lateral surfaces, the transistor essentially has four gates controlling the current through the channel region.